With the increasing down-scaling of integrated circuits and increasingly demanding requirements to the speed of integrated circuits, transistors need to have higher drive currents with increasingly smaller dimensions. Fin Field-Effect Transistors (FinFETs) were thus developed.
In the existing formation process of FinFETs, Shallow Trench Isolation (STI) regions are first formed in a semiconductor substrate. The STI regions are then recessed. As a result, a portion of the semiconductor substrate between two neighboring STI regions is over the top surfaces of the recessed STI regions. This portion of the semiconductor substrate thus forms a semiconductor fin, on which a FinFET is formed.
It was found that the STI regions may have a non-uniform property. For example, the upper portions of the STI regions often have a greater etching rate than the lower portions. This results in the difficulty in the control of the etching of the STI regions. Existing methods for reducing the etching rates of the upper portions of the STI regions include thermal anneal. However, the thermal anneal requires extra thermal budget, and may cause the wafer warpage.